As illustrated in example FIG. 1, a flash floating poly gate structure may be manufactured using schemes illustrated in example FIGS. 2A to 2D.
As illustrated in example FIG. 2A, a semiconductor process may be performed to form the active region of semiconductor substrate 201 (for example, a silicon substrate, a ceramic substrate, and a polymer substrate) and shallow trench isolation (STI) 203 for device isolation and to form tunnel oxide 205 in the active region on and/or over substrate 210.
As illustrated in example FIG. 2B, poly floating gate 207 may be formed on and/or over tunnel oxide 205.
As illustrated in example FIG. 2C, dielectric layer composed as oxide-nitride-oxide (ONO) layer 209 may be deposited on and/or over flowing gate 207.
As illustrated in example FIG. 2D, control gate 211 may then be deposited on and/or over the entire surface of semiconductor substrate 201 including ONO layer 209 to realize a flash floating poly gate.
However, in manufacturing the flash floating poly gate as illustrated in example FIGS. 1 and 2A to 2D, high integration may be obtained so that an area occupied by a capacitor in a flash memory device may be reduced, that the surface area of the capacitor may be reduced, and that a coupling ratio essential to the flash memory device may be significantly reduced to deteriorate the yield and reliability of the semiconductor device.